HEMT transistors (High Electron Mobility Transistors) made of III-N semiconductor materials are conventionally “normally on,” i.e., they have a negative threshold voltage and can conduct current with a gate voltage of OV. These components with negative threshold voltages are called depletion mode (or “D-Mode”) components.
It is preferable for power electronics applications to have so-called “normally off” components, i.e., to have a positive threshold voltage, which, therefore, cannot conduct current when the gate voltage is OV. These components are currently called enhancement mode (“E-mode”) components.
The manufacture of high voltage E-mode components on III-N semiconductor materials is complex. An alternative to a simple high voltage E-mode component is to combine a high voltage D-mode component with an E-mode, for example, low voltage component. Advantageously, the high voltage transistor is a HEMT transistor made of III-N semiconductor materials and the low voltage transistor is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) made of silicon.
For example, as shown in FIG. 1, chips 1, 2 comprising D-mode HEMT and MOSFET components respectively can be coupled to form a cascode-type integrated circuit 3: the drain 2a and the source 2b of the E-mode MOSFET chip 2 are respectively connected to the source 1b and the gate 1c of the HEMT D-mode chip 1; this electrical connection is provided in the housing 4 of the integrated circuit 3 including the two electronic chips 1, 2, usually by wire bonding 5 between different contact pads of the gate 1c, 2c, source 1b, 2b and drain 1a, 2a accessible on each of the chips 1, 2. In the integrated cascode circuit 3, the gate 2c of the MOSFET chip 2 controls the setting of the ON mode or the OFF mode of the integrated circuit 3.
The gate contact pad 2c of the MOSFET chip 2 is connected in the housing 4 of the integrated circuit 3 to a gate pin 3c. The source contact pad 2b of the MOSFET chip 2 is connected in the housing 4 to a source pin 3b. Eventually, the drain contact pad of the HEMT chip 1 is connected, still in the housing 4, to a drain pin 3a. Usually, the connections between the contact pads of the chips and the pins are provided by wire connection 5 or using electrical connection clips. The three pins 3a, 3b, 3c provide the electrical connections of the integrated circuit 3 outside the housing 4.
In a cascode-type integrated circuit, while fast switching is one of the expected benefits of a HEMT chip, interconnections (including wired connections) between the different components limit the switching speed. Indeed, the interconnections create parasitic overvoltages or undervoltages that can damage the different transistors during each switching. It is, therefore, necessary to reduce the switching edges (switching speed) to limit these excursions in parasitic voltage. To access high switching speeds, it is, therefore, necessary to minimize the inductances and parasitic resistances associated with interconnections in a cascode arrangement.
In addition, the fact that the two chips are side by side in the housing requires the use of an interconnection substrate (for example, DBC for “Direct bonded copper”) and increases the necessary lateral dimensions of the housing.
U.S. Pat. No. 8,847,408 presents a cascode-integrated circuit without an interconnection substrate comprising a first III-N transistor on which a second MOSFET transistor is stacked; the back side of the MOSFET transistor, which includes the drain contact pad of the MOSFET, is assembled on the source contact pad of the III-N transistor, on the front side of the latter. Although reducing the necessary lateral dimensions of the housing, this configuration has some disadvantages. In particular, the presence of inductances and parasitic resistances related to the electrical connections between the gate contact pad, the MOSFET source pads and the associated pins.